Magnetic disc drives have read/write heads, which are used for both writing data to magnetic disc and reading data from the magnetic disc. During a write operation, a write signal is provided to a selected read/write head from a write control circuit. The write signal represents data to be encoded onto the magnetic disc. More particularly, the read/write head receives encoded digital data from a "channel" chip. The transitions of the signal received from the channel chip cause the write current flowing within the read/write head to reverse direction which, in turn, induces a flux reversal in the magnetized material of the medium.
During a read operation, the read/write head senses these flux reversals from the magnetic disc. The flux reversals, as described hereinabove, had been encoded onto the magnetic disc during the write operation. Based on the flux reversals, the read/write head provides a read signal to the read circuit. The read channel amplifies the read signal and a channel circuit recovers the data that had been encoded. The channel circuit then provides the data to a magnetic disc controller for further processing.
Recent developments in high density read channel head technology have resulted in magneto-resistive (MR) heads which need bias currents up to 20 milli amps while delivering up to 20 micro voltage of signal amplitude. Even so, very low noise levels are still necessary to pick up much smaller signals while also being capable of handling relatively large signal swings at high frequencies. Miniaturization of tape and disc storage technology requires the integration of more than one preamplifier along with biasing capabilities for both read and bias MR heads.
FIG. 1 illustrates a single ended preamp integrated circuit 100. The single ended preamp IC 100 includes two MR channels 140 and 142. These channels are connected in a cascoded configuration. Although, two channels are illustrated, additional channels could be added to the cascoded configuration. MR channel 140 includes MR resistance 110, which corresponds to the resistive of the actual MR head. Each of the MR channels are controlled to the individually and selectively operative. More particularly, a current path through the magnetic resistance 110 is controlled by transistor 112. The switch 114 controls the transistor 112 by being connected to the base of the transistor 112. When the switch 114 is open the base is raised to a voltage which exceeds the threshold potential, this causes the transistor to enter the conduction state so that a conduction path is established between the emitter and collector. The switch 114 is controlled through control line 144. Normally, only one MR channel is activated at any one time. Other MR channels, for example, MR channel 142 may be activated by a different control sign to switch 124. The current path for the MR channel is connected to a common current path, which includes the load resistance 138 and common cascode transistor 130. The base of the common control transistor 130 is connected to a voltage source 132. The voltage source is sufficient so that transistor 130 operates in a triode state to provide the characteristics of the preamplifier desired. An advantage of this circuit is that many additional MR channels can be connected to the common cascode line 146. Further, a smaller size may be chosen for transistor 130, minimizing the parasitic capacitance 134 of transistor 130. This small capacitance results in a flat frequency response. However, when the number of MR channels is sufficiently large, a noise problem results, in that the parasitic capacitance 116 of transistor 112 in parallel with the parasitic capacitance 126 of transistor 122 and the parasitic capacitance of the other transistor and algebraically summed as the number of MR channels increase. This resulting summed capacitance presents a noise problem.
FIG. 2 illustrates another design configuration for multiple MR channels. With this design, each MR channel has a individual cascode transistor eliminating the need for the common cascode line 144 of FIG. 1. Without the common cascode line, the effect of parallel capacitance does not occur. The current path of the MR channel 240 includes a transistor 212 controlled by switch 214. Additionally, the MR channel 240 includes a cascode transistor 250 coupled to voltage source 254. The transistor 250 is coupled to the common R-Load 238 through the common load line 260. Since, the capacitance associated with transistor 212 is no longer directly connected to the corresponding transistors in other MR channels, there is no parallel connection, and consequently, no summing of capacitance. However, the cascode transistor 250 has an associated parasitic capacitance 252 connected to the common load line 260. With a number of MR channels connected in parallel to the common load line, these parasitic capacitances associated with each of the cascode transistors for each of the channels are connected in parallel and the effective impedance of these parallel, capacitances is achieved by algebraically summing the capacitance from each of the channels. The frequency response is proportional to 1/RC, where R is the resistive value of resistance 238 and C is the effective impedance. Thus, it can be very clearly seen that as the capacitance increases the frequency response from the preamplifier decreases. For a large number of these channels the high frequency response deteriorates quickly. Thus, both of the prior art circuits do not providing a substantially flat frequency response without a noise problem.